This application claims the priority of Application No. 2000-066703, filed Mar. 10, 2000 in Japan, the subject matter of which is incorporated herein by reference.
The present invention relates to a non-volatile memory such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory. The present invention also relates to a method for fabricating a non-volatile memory.
A conventional non-volatile memory is described, for example, in a Japanese Laying Open Publication H05-315622.
FIG. 1 shows a conventional non-volatile memory shown in the above-described Japanese publication. The non-volatile memory includes a p-type silicon substrate 1 having a square shape of cavity (groove) therein. The cavity is provided at a side wall and a bottom surface with an insulating layer 2 having a pass-through hole 2a at the center. On the inside wall of the insulating layer 2, a control gate electrode 3, an inter-gate insulating layer 4, a floating gate electrode 5 and an insulating layer 6 are formed in order toward the center of the cavity. A drain drawing electrode 7 is buried in the insulating layer 6.
A drain region 8 is formed under the pass-through hole 2a on the silicon substrate 1 so as to reach a region under the floating gate electrode 5. A source region 9 is formed around the cavity on the upper surface of the silicon substrate 1. In such a non-volatile memory, the insulating layer 2 is used as a tunnel oxide layer 2x at a region between the floating gate electrode 5 and the silicon substrate 1. Further, the insulating layer 2 is used as a gate insulating layer 2y at a region being in contact with the control gate electrode 3. A channel C is formed at a region radially extending from the bottom center of the cavity toward the upper surface of the silicon substrate 1.
In operation, in order to write data in the memory, the source region 9 is kept at 0V, and the drain region 8 and control gate electrode 3 are applied with a positive voltage to allow electric current flow through them. Thermoelectrons are generated around the drain region 8 and are implanted in the floating gate electrode 5 through the tunnel oxide layer 2x. In order to delete data stored in the memory, the control gate electrode 3 is kept at 0V, and the drain region 8 is applied with a positive voltage so that electrons are taken out of the floating gate electrode 5.
In order to read data out of the memory, a voltage (potential) is applied between the drain region 8 and source region 9, and the amount of electric current flowing through them is detected. If some electrons are implanted in the floating gate electrode 5, positive electric field of the control gate electrode 3 is reduced. As a result, no channel is made at the bottom surface of the cavity under the floating gate electrode 5 and only a small amount of electric current flows there. On the other hand, if no electron is implanted in the floating gate electrode 5, positive electric field of the control gate electrode 3 is applied to the silicon substrate 1 under the control gate electrode 3. As a result, a channel is made and a large amount of electric current flows there.
According to the above described Japanese publication, the conventional non-volatile memory uses a part of the insulating layer 2 as the tunnel oxide layer 2x. The insulating layer formed between the floating gate electrode 5 and control gate electrode 3 is used as an inter-gate insulating layer between floating gate and control gate. As a result, the memory provides a larger coupling ratio and higher efficient of writing and deleting characteristics. At the same time, the supply voltage may be reduced.
However, according to the conventional non-volatile memory, the tunnel oxide layer 2x formed between the drain region 8 and floating gate electrode 5 is arranged at the center of the cavity for a memory cell. It is required to align an end of the floating gate and the drain region with a high accuracy. In order to realize such a high accuracy of alignment, the floating gate 5 must be formed to have a larger thickness. The tunnel oxide layer 2x is formed in plane parallel to the silicon substrate. Therefore, it is difficult to improve integration of the memory.
Accordingly, an object of the present invention is to provide a non-volatile memory of which the integration can be improved easily without lowering the characteristics and reliability thereof.
Another object of the present invention is to provide a method for fabricating a non-volatile memory in which the integration of the memory can be improved easily without lowering the characteristics and reliability thereof.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, a non-volatile memory includes a substrate: a floating gate electrode and a control gate electrode formed on the substrate; and an active layer formed around the control gate and the floating gate. The active layer has source and drain and a channel layer between the source and drain.
The active layer may be formed to be overlapped with the floating gate electrode in a first direction, which is parallel to the silicon substrate. Other wise, the active layer is formed not to be overlapped completely with the floating gate electrode in the first direction.
According to a second aspect of the present invention, a method for fabricating a non-volatile memory includes the steps of providing a first conductive type of silicon substrate; etching the silicon substrate to form a groove extending two orthogonal directions in matrix; forming a cell isolating insulation layer in the groove; etching the silicon substrate to form a cavity for each memory cell and a first conductive type of active region on an inner surface of the cavity; forming a common source region on the silicon substrate entirely; forming a drain region on the active region; forming a first insulating layer on the common source region at the bottom of the cavity; forming a second insulating layer on an inner side surface of the cavity surrounded by the active region; forming a second conductive type of floating gate electrode on an inner side surface of the second insulating layer; forming a third insulating layer on an inner side surface of the floating gate electrode; and forming a second conductive type of control gate electrode in the cavity surrounded by the third insulating layer.
Another method includes the steps of: providing a first conductive type of silicon substrate; etching the silicon substrate to form a cavity for each memory cell and a first conductive type of active region left in the cavity; forming a common source region on the silicon substrate entirely and a drain region on the active region by a self alignment process; forming a gate insulating layer, a floating gate electrode, an inter-gate insulating layer and a control gate electrode are formed around the active region in order by a self alignment process; and forming a cell isolating insulation layer between two of the adjacent cavities.